Oscillator and clock generation circuit

ABSTRACT

Embodiments of the present application provide an oscillator and a clock generation circuit. The oscillator includes: a first ring topology, including a plurality of first inverters connected end to end, and configured to transmit an oscillation signal at a first transmission speed; and a second ring topology, including a plurality of second inverters connected end to end, and configured to transmit the oscillation signal at a second transmission speed, wherein the present application, the first ring topology is electrically connected to the second ring topology, and the second transmission speed is less than the first transmission speed.

CROSS-REFERENCE TO RELATED APPLICATIONS

This is a continuation of International Application No.PCT/CN2021/118858, filed on Sep. 16, 2021, which claims the priority toChinese Patent Application No. 202011173760.4, titled “OSCILLATOR ANDCLOCK GENERATION CIRCUIT” and filed on Oct. 28, 2020. The entirecontents of International Application No. PCT/CN2021/118858 and ChinesePatent Application No. 202011173760.4 are incorporated herein byreference.

TECHNICAL FIELD

Embodiments of the present application relate to, but are not limitedto, an oscillator and a clock generation circuit.

BACKGROUND

As a commonly used semiconductor memory in computers, a dynamic randomaccess memory (DRAM) is composed of many repeated memory cells. In aDRAM I/O circuit, a high-speed clock signal of a specific frequency isrequired for reading, writing, and clock calibration.

A ring oscillator may be used to generate a high-speed clock signalinside the DRAM, to meet the foregoing requirement. However, a frequencyof an oscillation signal generated by a current ring oscillator is low,which is difficult to meet the high speed requirement. In addition, thefrequency and a duty cycle of the oscillation signal generated by thecurrent ring oscillator are easily affected by a process, a supplyvoltage, a temperature, a clock load, and the like, causing deviationsin the clock frequency and the duty cycle.

SUMMARY

Embodiments of the present application provide an oscillator, including:a first ring topology, including a plurality of first invertersconnected end to end, and configured to transmit an oscillation signalat a first transmission speed; and a second ring topology, including aplurality of second inverters connected end to end, and configured totransmit the oscillation signal at a second transmission speed, wherethe first ring topology is electrically connected to the second ringtopology, and the second transmission speed is less than the firsttransmission speed.

The embodiments of the present application further provide a clockgeneration circuit, including: the oscillator described above; and afrequency adjustment module, connected to the oscillator, and configuredto adjust a frequency of the oscillator.

BRIEF DESCRIPTION OF THE DRAWINGS

One or more embodiments are exemplified by corresponding drawings, andthese exemplified descriptions do not constitute a limitation on theembodiments. Components with the same reference numerals in the drawingsare denoted as similar components, is and the drawings are not limitedby scale unless otherwise specified.

FIG. 1 is a schematic diagram of a circuit structure of an oscillatoraccording to an embodiment of the present application;

FIG. 2 is a schematic diagram of another circuit structure of anoscillator according to an embodiment of the present application;

FIG. 3 is a schematic structural diagram of a buffer inverter in theoscillator shown in FIG. 2 ;

FIG. 4 is a schematic structural diagram of a first inverter in theoscillator shown in FIG. 2 ;

FIG. 5 is a schematic structural diagram of a second inverter in theoscillator shown in FIG. 2 ;

FIG. 6 is another schematic structural diagram of the first inverter inthe oscillator shown in FIG. 2 ;

FIG. 7 is another schematic structural diagram of the second inverter inthe oscillator shown in FIG. 2 ; and

FIG. 8 is a schematic structural diagram of a clock generation circuitaccording to an embodiment of the present application.

DETAILED DESCRIPTION

In order to make the objectives, technical solutions and advantages ofthe embodiments of the present disclosure clearer, the embodiments ofthe present disclosure are described below with reference to theaccompanying drawings. Those of ordinary skill in the art shouldunderstand that many technical details are proposed in each embodimentof the present disclosure to help the reader better understand thepresent disclosure. However, even without these technical details andvarious changes and modifications made based on the followingembodiments, the technical solutions claimed in the present disclosuremay still be realized.

FIG. 1 is a schematic diagram of a circuit structure of an oscillatoraccording to an embodiment of the present application.

Referring to FIG. 1 , the oscillator includes: a first ring topology,including a plurality of first inverters 11 connected end to end, andconfigured to transmit an oscillation signal at a first transmissionspeed; and a second ring topology, including a plurality of secondinverters 12 connected end to end, and configured to transmit theoscillation signal at a second transmission speed. The first ringtopology is electrically connected to the second ring topology, and thesecond transmission speed is less than the first transmission speed.

The transmission speed refers to a time for the oscillation signal tochange from a high level to a low level or from a low level to a highlevel. A lower transmission speed indicates a longer transmission time,and a lower flip speed of the oscillation signal indicates a longerperiod and a lower frequency of the oscillation signal. A highertransmission speed indicates a shorter transmission time, and a higherflip speed of the oscillation signal indicates a shorter period and ahigher frequency of the oscillation signal. That the second transmissionspeed is less than the first transmission speed means that thetransmission time of the oscillation signal through the second inverter12 is shorter than the transmission time of the oscillation signalthrough the first inverter 11.

In some embodiments, a quantity of the first inverters 11 is N, and N isan integer greater than or equal to 4. Correspondingly, a quantity ofthe second inverters 12 is M, and M is an integer greater than or equalto 2.

An input terminal of each first inverter 11 is denoted as a first node,and the first ring topology has N first nodes. For example, the firstnodes are clk360, clk270, clk180, and clk90 in FIG. 1 . An inputterminal of each second inverter 12 is denoted as a second node, and thesecond ring topology has M second nodes. For example, the second nodesare clk360′ and clk180′ in FIG. 1 . At least two second nodes areelectrically connected to a corresponding quantity of first nodes. Forexample, in FIG. 1 , clk360′ is connected to clk360 and clk180′ isconnected to clk180.

On an oscillation path of the first ring topology, each first node has adifferent phase. For example, there are four first inverters 11, fourfirst nodes on the oscillation path respectively have a first phaseclk90, a second phase clk180, a third phase clk270, and a fourth phaseclk360, and the four first nodes constitute an oscillation cycle of 360degrees, that is, each first node corresponds to a phase shift of 90degrees. Correspondingly, the second ring topology has two second nodes:one is the second node is clk180′, electrically connected to the firstnode having the second phase clk180, and the other is the second nodeclk360′, electrically connected to the first node having the fourthphase clk360.

In some embodiments, the second transmission speed is less than thefirst transmission speed, and the second transmission speed is greaterthan or equal to 0.5 times the first transmission speed. Thetransmission speed may be understood as being inversely proportional toa transmission delay of the inverter. For example, it is assumed thatthe transmission speed of the oscillation signal through the firstinverter 11 is 100. In this case, the transmission speed of theoscillation signal through the second inverter 12 is greater than orequal to 50 and less than 100. For another example, it is assumed that atransmission delay of the oscillation signal through the first inverter11 is 100 picoseconds (ps). In this case, the transmission delay of theoscillation signal through the second inverter 12 is greater than 100 psand less than or equal to 200 ps. Such a setting can improve stabilityof the oscillator and quality of the oscillation signal.

In some embodiments, referring to FIG. 2 , the oscillator may furtherinclude: a third ring topology, including a plurality of third inverters13 connected end to end, and configured to transmit the oscillationsignal at a third transmission speed. The first ring topology iselectrically connected to the third ring topology, and the thirdtransmission speed is less than the first transmission speed.

The first ring topology is used as an outer ring topology. The secondring topology and the third ring topology are used as inner ringtopologies. Inverter quantities of different ring topology structuresmay be specifically as follows: a quantity of the first inverters 11 isU, and U is an integer greater than or equal to 4; a quantity of thesecond inverters 12 is V, and V is an integer greater than or equal to2; and a quantity of the third inverters 13 is W, and W is an integergreater than or equal to 2.

An input terminal of each first inverter 11 is denoted as a first node,and the first ring topology has U first nodes. For example, the firstnodes are clk360, clk270, clk180, and clk90 in FIG. 2 . An inputterminal of each second inverter 12 is denoted as a second node, and thesecond ring topology has V second nodes. For example, the second nodesare clk360′ and clk180′ in FIG. 2 . An input terminal of each thirdinverter 13 is denoted as a is third node, and the third ring topologyhas W third nodes. For example, the second nodes are clk270′ and clk90′in FIG. 2 . At least two second nodes are electrically connected to acorresponding quantity of first nodes. At least two third nodes areelectrically connected to a corresponding quantity of first nodes. Forexample, in FIG. 2 , clk360′ is connected to clk360, clk270′ isconnected to clk270, clk180′ is connected to clk180, and clk90′ isconnected to clk90. In this way, oscillation signals of different firstnodes have larger quantities of flips per unit time, thus improving thefrequency of the transmitted oscillation signal, thereby improving thetransmission speed of the oscillation signal.

In some embodiments, the second transmission speed is less than thefirst transmission speed, the second transmission speed is greater thanor equal to 0.5 times the first transmission speed, and the thirdtransmission speed is equal to the second transmission speed. Thetransmission speed may be understood as being inversely proportional toa transmission delay of the inverter. For example, it is assumed thatthe transmission speed of the oscillation signal through the firstinverter 11 is 100. In this case, the transmission speed of theoscillation signal through the second inverter 12 is greater than orequal to 50 and less than 100. For another example, it is assumed that atransmission delay of the oscillation signal through the first inverter11 is 100 picoseconds (ps). In this case, the transmission delay of theoscillation signal through the second inverter 12 is greater than 100 psand less than or equal to 200 ps. Such a setting can improve stabilityof the oscillator and quality of the oscillation signal.

In some embodiments, the oscillator further includes a buffer inverter14, an input terminal of the buffer inverter 14 receives the oscillationsignal, and an output terminal of the buffer inverter 14 outputs a clocksignal. The buffer inverter 14 is configured to isolate an impact of aback-end circuit (such as a duty cycle calibration circuit) of theoscillator as a load on the frequency of the oscillation signal, suchthat the oscillator maintains a high multiplexing rate.

In some embodiments, a transmission speed of the buffer inverter 14 isadjustable. For example, the transmission speed of the buffer inverter14 is adjustable by adjusting a pull-up capability and/or a pull-downcapability of the buffer inverter 14.

The pull-down capability of the buffer inverter 14 is decreased when thepull-up capability of the buffer inverter 14 is increased. The pull-downcapability of the buffer inverter 14 is increased when the pull-upcapability of the buffer inverter 14 is decreased.

The pull-up capability refers to a capability of charging a low-levelsignal to a high-level signal. The pull-down capability refers to acapability of discharging a high-level signal to a low-level signal. Aduty cycle of the clock signal output by the buffer inverter 14 isincreased when the pull-up capability is increased and the pull-downcapability is decreased. The duty cycle of the clock signal output bythe buffer inverter 14 is decreased when the pull-up capability isdecreased and the pull-down capability is increased. In other words, theduty cycle of the clock signal is adjustable by controlling the pull-upcapability and the pull-down capability of the buffer inverter 14 tochange toward different trends, such that the duty cycle of the clocksignal meets a preset requirement. It should be noted that, each firstnode can be connected to a buffer inverter 14, or a buffer inverter 14can be connected in series between each first node and the back-endcircuit to avoid an impact of the back-end circuit on the frequency ofthe oscillation signal, to ensure that each stage of the first inverter11 of the oscillator has a high degree of load matching, such that thefrequency of the oscillation signal of the oscillator is more stable.For example, in FIG. 2 , clk360, clk270, clk180, and clk90 are eachconnected to a buffer inverter 14.

For example, referring to FIG. 3 , the buffer inverter 14 includes: afirst PMOS group 141, including H PMOSs (MPH1, MPH2, . . . , and MPHn),where a source of each of the H PMOSs is connected to a power terminalVcc; a first NMOS group 142, including H NMOSs (MNH1, MNH2, . . . , andMNHn), where a source of each of the H NMOSs is connected to a groundterminal Vss; a zeroth PMOS MPH0, having a source connected to a drainof each of the H PMOSs; and a zeroth NMOS MNH0, having a sourceconnected to a drain of each of the H NMOSs. A drain of the zeroth PMOSMPH0 is connected to a drain of the zeroth NMOS MNH0, as the outputterminal clkout of the buffer inverter 14. A gate of the zeroth PMOSMPH0 is connected to a gate of the zeroth NMOS MNH0, as the inputterminal clkin of the buffer inverter 14. A gate of each of the H PMOSsand a gate of each of the H NMOSs are both controlled by a duty cycleadjustment code group (Dcc1, Dcc2, . . . , and Dccn).

The duty cycle adjustment code group may be sent by a duty cycleadjustment module (not shown in the figure), and a PMOS and a PMOStransistor are each a PMOS transistor.

In some embodiments, a quantity of turned-on PMOS transistors in thefirst PMOS group 141 and/or a quantity of turned-on NMOS transistors inthe first NMOS group 142 can be controlled by controlling parameters ofthe duty cycle adjustment code group, thereby adjusting the pull-upcapability and/or the pull-down capability of the buffer inverter 14.

It should be noted that, the PMOS transistor and the NMOS transistorhave different turn-on voltages. For example, when the first adjustmentcode Dcc1 in the duty cycle adjustment code group is at a high level,the first NMOS transistor MNH1 is turned on and the first PMOStransistor MPH1 is turned off; and when the first adjustment code Dcc1is at a low level, the first NMOS transistor MNH1 is turned off and thefirst PMOS transistor MPH1 is turned on.

A duty cycle adjustment code simultaneously controls the first PMOSgroup 141 and the first NMOS group 142. Therefore, a larger quantity ofturned-on PMOS transistor in the first PMOS group 141 indicates asmaller quantity of turned-on NMOS transistors in the first NMOS group142. A larger quantity of turned-on PMOS transistors in the first PMOSgroup 141 indicates a smaller load value of the first PMOS group 141, ahigher charging rate of the buffer inverter 14, and a stronger pull-upcapability of the buffer inverter 14. Correspondingly, a smallerquantity of turned-on NMOS transistors in the first NMOS group 142indicates a larger load value of the first NMOS group 142, a lowerdischarging rate of the buffer inverter 14, and a weaker pull-downcapability of the buffer inverter 14. In this way, when a large quantityof PMOS transistors are turned on and a small quantity of NMOStransistors are turned on, the duty cycle of the clock signal output bythe buffer inverter 14 is increased.

Correspondingly, when a small quantity of PMOS transistors are turned onand a large quantity of NMOS transistors are turned on, the pull-upcapability of the buffer inverter 14 is decreased and the pull-downcapability is increased, and the duty cycle of the clock signal outputby the buffer inverter 14 is decreased.

In order to ensure normal operation of the zeroth PMOS MPH0 and thezeroth NMOS MNH0, an initial PMOS transistor MPHs and an initial NMOStransistor MNHs are further provided. The initial PMOS transistor MPHshas a source connected to the power terminal Vcc, a drain connected tothe source of the zeroth PMOS MPH0, and a gate connected to the groundterminal Vss, that is, the initial PMOS transistor MPHs is turned on.The initial NMOS transistor MNHs has a source connected to the groundterminal Vss, a drain connected to the source of the zeroth NMOS MNH0,and a gate connected to the power terminal Vcc, that is, the initialNMOS transistor MNHs is turned on.

In some embodiments, the first transmission speed of the first inverter11 is adjustable. The first transmission speed of the first inverter 11is adjustable by adjusting a pull-up capability and/or a pull-downcapability of the first inverter 11.

The pull-down capability of the first inverter 11 is increased when thepull-up capability of the first inverter 11 is increased. The pull-downcapability of the first inverter 11 is decreased when the pull-upcapability of the first inverter 11 is decreased. In this way, thefrequency of the oscillation signal output by the oscillator can beadjusted, to obtain an oscillation signal meeting a preset frequencyrequirement.

For example, referring to FIG. 4 , the first inverter 11 includes: athird PMOS group 111, including I PMOSs (MPI1, MPI2, . . . , and MPIn),where a source of each of the I PMOSs is connected to a power terminalVcc; a third NMOS group 112, including I NMOSs (MNI1, MNI2, . . . , andMNIn), where a source of each of the I NMOSs is connected to a groundterminal Vss; a second PMOS MPI0, having a source connected to a drainof each of the I PMOSs; and a second NMOS MNI0, having a sourceconnected to a drain of each of the I NMOSs. A drain of the second PMOSMPI0 is connected to a drain of the second NMOS MNI0, as an outputterminal of the first inverter 11. A gate of the second PMOS MPI0 isconnected to a gate of the second NMOS MNI0, as an input terminal of thefirst inverter 11. A gate of each of the I PMOS transistors iscontrolled by a first reverse adjustment code group (enb11, enb12, . . ., and enb1 n). A gate of each of the I NMOSs is controlled by a firstpositive adjustment code group (en11, en12, . . . , and en1 n). Thefirst transmission speed is adjustable changing the first reverseadjustment code group and/or the first positive adjustment code group.

In some embodiments, a quantity of turned-on PMOS transistors in thethird PMOS group 111 can be controlled by controlling parameters of thefirst reverse adjustment code group, thereby adjusting the pull-upcapability of the first inverter 11; and/or a quantity of turned-on NMOStransistors in the third NMOS group 112 can be controlled by controllingparameters of the first positive adjustment code group, therebyadjusting the pull-down capability of the first inverter 11.

It should be noted that, the first reverse adjustment code group and thefirst positive adjustment code group have opposite potentials, that is,opposite phases. When the first positive adjustment code en11 is at ahigh level, the first reverse adjustment code enb11 is at a low level.In this case, the first PMOS transistor MPI1 in the third PMOS group 111is turned on, and the first NMOS transistor MNI1 in the third NMOS group112 is turned on. Correspondingly, when the first positive adjustmentcode en11 is at a low level, the first reverse adjustment code enb11 isat a high level. In this case, the first PMOS transistor MPI1 in thethird PMOS group 111 is turned off, and the first NMOS transistor MNI1in the third NMOS group 112 is turned off.

In other words, a larger quantity of turned-on PMOS transistors in thethird PMOS group 111 indicates a larger quantity of turned-on NMOStransistors in the third NMOS group 112, a stronger pull-up capabilityand a stronger pull-down capability of the first inverter 11, and ahigher frequency of the oscillation signal output by the first inverter11. Correspondingly, a smaller quantity of turned-on PMOS transistors inthe third PMOS group 111 indicates a smaller quantity of turned-on NMOStransistors in the third NMOS group 112, a weaker pull-up capability anda weaker pull-down capability of the first inverter 11, and a lowerfrequency of the oscillation signal output by the first inverter 11.

In addition, the first inverter 11 has an initial PMOS transistor MPIsfor ensuring that the second PMOS MPI0 is in a working state, and aninitial NMOS transistor MNIs for ensuring that the second NMOS MNI0 isin a working state.

In some embodiments, a second transmission speed of the second inverter12 is adjustable. The second transmission speed of the second inverter12 is adjustable by adjusting a pull-up capability and/or a pull-downcapability of the second inverter 12.

The pull-down capability of the second inverter 12 is increased when thepull-up capability of the second inverter 12 is increased. The pull-downcapability of the second inverter 12 is decreased when the pull-upcapability of the second inverter 12 is decreased.

For example, referring to FIG. 5 , the second inverter 12 includes: afifth PMOS group 121, including L PMOSs (MPL1, MPL2, . . . , and MPLn),where a source of each of the L PMOSs is connected to a power terminalVcc; a fifth NMOS group 122, including L NMOSs (MNL1, MNL2, . . . , andMNLn), where a source of each of the L NMOSs is connected to a groundterminal Vss; a fourth PMOS MPL0, having a source connected to a drainof each of the L PMOSs; and a fourth NMOS MNL0, having a sourceconnected to a drain of each of the L NMOSs. A drain of the fourth PMOSMPL0 is connected to a drain of the fourth NMOS MNL0, as an outputterminal of the second inverter 12. A gate of the fourth PMOS MPL0 isconnected to a gate of the fourth NMOS MNL0, as an input terminal of thesecond inverter 12. A gate of each of the L PMOS transistors iscontrolled by a second reverse adjustment code group (enb21, enb22, . .. , and enb2 n). A gate of each of the L NMOSs is controlled by a secondpositive adjustment code group (en21, en22, . . . , and en2 n). Thefirst transmission speed is adjustable by changing the second reverseadjustment code group and/or the second positive adjustment code group.

In some embodiments, a quantity of turned-on PMOS transistors in thefifth PMOS group 121 can be controlled by controlling parameters of thesecond reverse adjustment code group, thereby adjusting the pull-upcapability of the second inverter 12; and/or a quantity of turned-onNMOS transistors in the fifth NMOS group 122 can be controlled bycontrolling parameters of the second positive adjustment code group,thereby adjusting the pull-down capability of the second inverter 12.

It should be noted that, the second reverse adjustment code group andthe second positive adjustment code group have opposite potentials. Whenthe second positive adjustment code en21 is at a high level, the secondreverse adjustment code enb21 is at a low level. In this case, the firstPMOS transistor MPL1 in the fifth PMOS group 121 is turned on, and thefirst NMOS transistor MNL1 in the fifth NMOS group 122 is turned on.Correspondingly, when the second positive adjustment code en21 is at alow level, the second reverse adjustment code enb21 is at a high level.In this case, the first PMOS is transistor MPL1 in the fifth PMOS group121 is turned off, and the first NMOS transistor MNL1 in the fifth NMOSgroup 122 is turned off.

In other words, a larger quantity of turned-on PMOS transistors in thefifth PMOS group 121 indicates a larger quantity of turned-on NMOStransistors in the fifth NMOS group 122, a stronger pull-up capabilityand a stronger pull-down capability of the second inverter 12, and ahigher frequency of the oscillation signal output by the second inverter12. Correspondingly, a smaller quantity of turned-on PMOS transistors inthe fifth PMOS group 121 indicates a smaller quantity of turned-on NMOStransistors in the fifth NMOS group 122, a weaker pull-up capability anda weaker pull-down capability of the second inverter 12, and a lowerfrequency of the oscillation signal output by the second inverter 12.

In addition, the second inverter 12 has an initial PMOS transistor MPLsfor ensuring that the fourth PMOS MPL0 is in a working state, and aninitial NMOS transistor MNLs for ensuring that the fourth NMOS MNL0 isin a working state.

In some embodiments, referring to FIG. 6 , the first inverter 11includes a plurality of first sub-inverters 113, input terminals of theplurality of first sub-inverters 113 are all electrically connected, andoutput terminals of the plurality of first sub-inverters 113 are allelectrically connected. This is beneficial to control a length of aconnection wire between another component in an oscillator layout designand the first sub-inverter 113 to be close or equal, such that theoscillator layout has a better symmetrical balance, and each key node ofthe oscillator in the layout has a high degree of load matching, therebymaking delays of all stages of inverters equal. In addition, this isalso beneficial to make the length of the connection wire between theanother component and the first sub-inverter 113 shorter, therebyreducing a parasitic resistance and a parasitic capacitance of theconnection wire, and making the oscillator have favorable performance.

The quantity of the first sub-inverters 113 is an even number, which isbeneficial to better symmetrical and balanced layout design.

In some embodiments, referring to FIG. 7 , the second inverter 12includes a plurality of second sub-inverters 123, input terminals of theplurality of second sub-inverters 123 are all electrically connected,and output terminals of the plurality of second sub-inverters 123 areall electrically connected. This is beneficial to improve thesymmetrical balance of the oscillator layout.

The quantity of the second sub-inverters 123 is equal to the quantity ofthe first sub-inverters 113. This is beneficial to improve thesymmetrical balance of the oscillator layout, thereby obtaining anoscillator with better performance.

Referring to FIG. 4 , FIG. 5 , FIG. 6 , and FIG. 7 , the first inverter11 and the second inverter 12 can be set to the same structure and size,and then transmission rates can be made different by using the firstreverse adjustment code group and/or the second positive adjustment codegroup, and the second reverse adjustment code group and/or the secondpositive adjustment code group.

In some embodiments, compared with transmitting the oscillation signalonly through the first ring topology, the setting of the second ringtopology can increase a quantity of inversions of the oscillation signalper unit time at electrically connected nodes, thereby obtaining ahigh-speed oscillation signal.

Correspondingly, an embodiment of the present application furtherprovides a clock generation circuit, including the oscillator providedin any one of the foregoing embodiments. FIG. 8 is a schematicstructural diagram of a clock generation circuit according to anembodiment of the present application. The following describes the clockgeneration circuit in detail with reference to the accompanyingdrawings. For parts that are the same as or corresponding to those inthe foregoing embodiments, reference may be made to the descriptions ofthe foregoing embodiments. Details are not described again below.

Referring to FIG. 8 , the clock generation circuit includes: anoscillator 20; and a frequency adjustment module 21, connected to theoscillator 20, and configured to adjust a frequency of the oscillator20.

The frequency adjustment module 21 adjusts a frequency of theoscillation signal of the oscillator 20 by adjusting the firsttransmission speed and/or the second transmission speed.

It can be understood that, the frequency adjustment module 21 can adjustthe frequency of the oscillation signal of the oscillator 20 byadjusting the first transmission is speed and the second transmissionspeed. The frequency adjustment module 21 adjusts the first transmissionspeed of the first inverter 11 and the second transmission speed of thesecond inverter 12 to adjust the frequency of the oscillation signal ofthe oscillator 20, or the frequency adjustment module 21 may adjust oneof the first transmission speed or the second transmission speed toadjust the frequency of the oscillation signal of the oscillator.Correspondingly, the frequency adjustment module 21 adjusts the firsttransmission speed of the first inverter 11 to adjust the frequency ofthe oscillation signal of the oscillator 20, or the frequency adjustmentmodule 21 adjusts the second transmission speed of the second inverter12 to adjust the frequency of the oscillation signal of the oscillator20.

In some embodiments, for example, the frequency adjustment module 21adjusts both the first transmission speed and the second transmissionspeed. The frequency adjustment module 21 is connected to the firstinverter 11 and the second inverter 12. The frequency adjustment module21 can adjust the first reverse adjustment code group to change thepull-up capability of the first inverter 11, and adjust the firstpositive adjustment code group to change the pull-down capability of thefirst inverter 11, thereby adjusting the first transmission speed of thefirst inverter 11, and adjusting the frequency of the oscillation signalof the oscillator 20. Correspondingly, the frequency adjustment module21 can adjust the second reverse adjustment code group to change thepull-up capability of the second inverter 12, and adjust the secondpositive adjustment code group to change the pull-down capability of thesecond inverter 12, thereby adjusting the second transmission speed ofthe second inverter 12, and adjusting the frequency of the oscillationsignal of the oscillator 20.

In other embodiments, the frequency adjustment module can be connectedto the first inverter or the second inverter, and can change only thepull-up capability or the pull-down capability of the first inverter, orcan change only the pull-up capability or the pull-down capability ofthe second inverter.

In some embodiments, the clock generation circuit further includes aduty cycle adjustment module 22, connected to the oscillator 20, andconfigured to adjust a duty cycle of the oscillation signal. Theoscillator 20 includes the buffer inverter 14. The buffer inverter 14 isconfigured to receive the oscillation signal and output the clocksignal. The duty cycle adjustment module 22 is connected to the bufferinverter 14. The duty cycle adjustment module 22 adjusts the pull-upcapability and the pull-down capability of the buffer inverter 14 byadjusting the parameters of the duty cycle adjustment code group, suchthat the pull-up capability and the pull-down capability of the bufferinverter 14 change toward different regions, thereby adjusting the dutycycle of the clock signal.

In other embodiments, the duty cycle adjustment module can also beconnected to the first inverter and/or the second inverter to adjust theduty cycle of the oscillation signal output by the first inverter and/orthe second inverter, such that the oscillation signal output by theoscillator meets a preset duty cycle requirement.

In some embodiments, the clock generation circuit can reduce an impactof a clock load on a frequency and a duty cycle of a high-speed clocksignal, thereby outputting a clock signal meeting a preset frequencyrequirement and a preset duty cycle requirement.

Those of ordinary skill in the art can understand that the aboveimplementations are specific embodiments for implementing the presentapplication. In practical applications, various changes may be made tothe above embodiments in terms of form and details without departingfrom the spirit and scope of the present application. Any person skilledin the art may make changes and modifications to the embodiments withoutdeparting from the spirit and scope of the present disclosure.Therefore, the protection scope of the present disclosure should besubject to the scope defined by the claims.

The invention claimed is:
 1. An oscillator, comprising: a first ringtopology, comprising a plurality of first inverters connected end toend, and configured to transmit an oscillation signal at a firsttransmission speed; and a second ring topology, comprising a pluralityof second inverters connected end to end, and configured to transmit theoscillation signal at a second transmission speed, wherein the firstring topology is electrically connected to the second ring topology, thesecond transmission speed is less than the first transmission speed, thefirst transmission speed is adjustable, the first transmission speed isadjustable by adjusting at least one of a pull-up capability or apull-down capability of the plurality of first inverters, the pull-downcapability of the plurality of first inverters is increased when thepull-up capability of the plurality of first inverters is increased, andthe pull-down capability of the plurality of first inverters isdecreased when the pull-up capability of the plurality of firstinverters is decreased.
 2. The oscillator according to claim 1, whereina quantity of first inverters in the plurality of first inverters is N,and N is an integer greater than or equal to
 4. 3. The oscillatoraccording to claim 2, wherein a quantity of second inverters in theplurality of second inverters is M, and M is an integer greater than orequal to
 2. 4. The oscillator according to claim 3, wherein an inputterminal of each first inverter is denoted as a first node, and thefirst ring topology has N first nodes; an input terminal of each secondinverter is denoted as a second node, and the second ring topology has Msecond nodes; and at least two second nodes are electrically connectedto a corresponding quantity of the first nodes.
 5. The oscillatoraccording to claim 1, further comprising: a third ring topology,comprising a plurality of third inverters connected end to end, andconfigured to transmit the oscillation signal at a third transmissionspeed, wherein the first ring topology is electrically connected to thethird ring topology, and the third transmission speed is less than orequal to the first transmission speed.
 6. The oscillator according toclaim 5, wherein a quantity of first inverters in the plurality of firstinverters is U, and U is an integer greater than or equal to 4; aquantity of second inverters in the plurality of second inverters is V,and V is an integer greater than or equal to 2; and a quantity of thirdinverters in the plurality of third inverters is W, and W is an integergreater than or equal to
 2. 7. The oscillator according to claim 6,wherein an input terminal of each first inverter is denoted as a firstnode, and the first ring topology has U first nodes; an input terminalof each second inverter is denoted as a second node, and the second ringtopology has V second nodes; an input terminal of each third inverter isdenoted as a third node, and the third ring topology has W third nodes;and at least two second nodes are electrically connected to acorresponding quantity of the first nodes, and at least two third nodesare electrically connected to a corresponding quantity of the firstnodes.
 8. The oscillator according to claim 7, wherein the thirdtransmission speed is equal to the second transmission speed.
 9. Theoscillator according to claim 1, further comprising: a buffer inverter,wherein an input terminal of the buffer inverter receives theoscillation signal, and an output terminal of the buffer inverteroutputs a clock signal; wherein a transmission speed of the bufferinverter is adjustable; the transmission speed of the buffer inverter isadjustable by adjusting at least one of a pull-up capability or apull-down capability of the buffer inverter; the pull-down capability ofthe buffer inverter is decreased when the pull-up capability of thebuffer inverter is increased; and the pull-down capability of the bufferinverter is increased when the pull-up capability of the buffer inverteris decreased.
 10. The oscillator according to claim 9, wherein thebuffer inverter comprises: a first P-channel metal-oxide semiconductor(PMOS) group, comprising H PMOSs, wherein a source of each of the HPMOSs is connected to a power terminal; a first N-channel metal-oxidesemiconductor (NMOS) group, comprising H NMOSs, wherein a source of eachof the H NMOSs is connected to a ground terminal; a zeroth PMOS, havinga source connected to a drain of each of the H PMOSs; and a zeroth NMOS,having a source connected to a drain of each of the H NMOSs, wherein adrain of the zeroth PMOS is connected to a drain of the zeroth NMOS, asthe output terminal of the buffer inverter; a gate of the zeroth PMOS isconnected to a gate of the zeroth N MOS, as the input terminal of thebuffer inverter; and a gate of each of the H PMOSs and a gate of each ofthe H NMOSs are both controlled by a duty cycle adjustment code group.11. The oscillator according to claim 1, wherein each of the pluralityof first inverters comprises: a third P-channel metal-oxidesemiconductor (PMOS) group, comprising I PMOSs, wherein a source of eachof the I PMOSs is connected to a power terminal; a third N-channelmetal-oxide semiconductor (NMOS) group, comprising I NMOSs, wherein asource of each of the I NMOSs is connected to a ground terminal; asecond PMOS, having a source connected to a drain of each of the IPMOSs; and a second NMOS, having a source connected to a drain of eachof the I NMOSs, wherein a drain of the second PMOS is connected to adrain of the second NMOS, as an output terminal of the first inverter; agate of the second PMOS is connected to a gate of the second N MOS, asan input terminal of the first inverter; a gate of each of the I PMOSsis controlled by a first reverse adjustment code group, and a gate ofeach of the I NMOSs is control led by a first positive adjustment codegroup; and the first transmission speed is adjustable by changing atleast one of the first reverse adjustment code group or the firstpositive adjustment code group.
 12. The oscillator according to claim 1,wherein the second transmission speed is adjustable; The secondtransmission speed is adjustable by adjusting at least one of a pull-upcapability or a pull-down capability of the plurality of secondinverters; the pull-down capability of the plurality of second invertersis increased when the pull-up capability of the plurality of secondinverters is increased; and the pull-down capability of the plurality ofsecond inverters is decreased when the pull-up capability of theplurality of second inverters is decreased.
 13. The oscillator accordingto claim 12, wherein each of the plurality of second inverterscomprises: a fifth P-channel metal-oxide semiconductor (PMOS) group,comprising L PMOSs, wherein a source of each of the L PMOSs is connectedto a power terminal; a fifth N-channel metal-oxide semiconductor (N MOS)group, comprising L NMOSs, wherein a source of each of the L NMOSs isconnected to a ground terminal; a fourth PMOS, having a source connectedto a drain of each of the L PMOSs; and a fourth NMOS, having a sourceconnected to a drain of each of the L NMOSs, wherein a drain of thefourth PMOS is connected to a drain of the fourth NMOS, as an outputterminal of the second inverter; a gate of the fourth PMOS is connectedto a gate of the fourth NMOS, as an input terminal of the secondinverter; a gate of each of the L PMOSs is controlled by a secondreverse adjustment code group, and a gate of each of the L NMOSs iscontrolled by a second positive adjustment code group; and the secondtransmission speed is adjustable by changing at least one of the secondreverse adjustment code group or the second positive adjustment codegroup.
 14. The oscillator according to claim 1, wherein each of theplurality of first inverters comprises a plurality of firstsub-inverters, input terminals of the plurality of first sub-invertersare all electrically connected, and output terminals of the plurality offirst sub-inverters are all electrically connected.
 15. The oscillatoraccording to claim 1, wherein each of the plurality of second inverterscomprises a plurality of second sub-inverters, input terminals of theplurality of second sub-inverters are all electrically connected, andoutput terminals of the plurality of second sub-inverters are allelectrically connected.
 16. A clock generation circuit, comprising: theoscillator according to claim 1; and a frequency adjustment module,connected to the oscillator, and configured to adjust a frequency of theoscillator.
 17. The clock generation circuit according to claim 16,wherein the frequency adjustment module adjusts a frequency of theoscillation signal of the oscillator by adjusting at least one of thefirst transmission speed or the second transmission speed; wherein thefrequency adjustment module adjusts the at least one of the firsttransmission speed of the plurality of first inverters or the secondtransmission speed of the plurality of second inverters to adjust afrequency of the oscillation signal of the oscillator.
 18. The clockgeneration circuit according to claim 16, further comprising: a dutycycle adjustment module, connected to the oscillator, and configured toadjust a duty cycle of the oscillation signal.
 19. The oscillatoraccording to claim 1, wherein the second transmission speed is greaterthan or equal to 0.5 times the first transmission speed.